In the ASM chart in Figure 7.41, we specify the assignment Cj ← Ci in state S2, and then in state S3 we increment Cj by 1. Is it possible to eliminate state S3 if the assignment Cj ← Ci + 1 is performed in S2? Explain any implications that this change has on the control and datapath circuits.

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Load registers C₁ C₁ + 1 C₁+C; +1 S2 S1 S3 A-R₁, C₁+C; S4 Reset C₁-0 C;+C; +1 S5 S S8 H B+R; B