A sequential circuit is shown in Figure 4-49. The timing parameters for the gates and lip- lops are as follows:

Figure 4-49:

(a) Find the longest path delay from an external circuit input passing through gates only to an external circuit output.

b) Find the longest path delay in the circuit from an external input to positive clock edge.

(c) Find the longest path delay from positive clock edge to output.

(d) Find the longest path delay from positive clock edge to positive clock edge.

(e) Determine the maximum frequency of operation of the circuit in megahertz (MHz).

Transcribed Image Text:

Inverter: tpd XOR gate: fpd Flip-flop: tpd = = 0.01 ns 0.04 ns 0.08 ns, ts = = 0.02 ns, and th = 0.01 ns