Questions and Answers of Logic And Computer Design Fundamentals

A set-dominant master-slave flip-flop has set and reset inputs. It differs from a conventional master-slave \(S R\) flip-flop in that, when both \(S\) and \(R\) are equal to 1 , the flip-flop is
Do a manual verification of the solution (either yours or the one posted on the text website) to Problem 27. Consider all transitions where \(S\) and \(R\) change with the clock equal to 0.Data From
Obtain a timing diagram similar to Figure 10 for a positive-edge-triggered \(J K\) flip-flop during four clock pulses. Show the timing signals for \(C, J, K, Y\), and \(Q\). Assume that initially the
Design the sequential circuit for the state-machine diagram from Problem 37. You may either solve Problem 37 or find its solution on the textbook website. Use a 1-hot state assignment, \(D\)
Repeat Problem 40 by using a VHDL process containing if-then-else statements.Data From Problems 40 40. *Write a VHDL description for the multiplexer in below figure by using a process containing a
Repeat Problem 48 by using a Verilog process containing if-else statements.Data From Problem 48 48. Write a Verilog description for the multiplexer in the above figure by using a process containing a
Write a Verilog description for a \(J K\) negative-edge-triggered flip-flop with clock \(C L K\). Compile and simulate your description. Apply a sequence that causes all eight combinations of inputs
Write a Verilog description for the state-machine diagram for the batch mixing system derived in Example 11.Data From Example 11. EXAMPLE 11 State-Machine Design of a Sliding Door Control Automatic
Repeat Problem 18, using a PAL device.Data From Problem 18 18. List the PLA equations for programming a BCD-to-excess-3 code converter. If necessary to reduce product terms, share product terms
Write a program to evaluate the arithmetic expression\[X=(A+B-C) \times(D-E)\]Make effective use of the registers to minimize the number of MOVE or LD instructions where possible.(a) Assume a
Repeat Problem 1 for\[Y=(A+B) \times C \div(D-E \times F)\]All operands are initially in memory. The operand order for divide, DIV, is quotient, dividend, divisor.Data From Problem 1 1. Based on
Given that \(A \cdot B=0\) and \(A+B=1\), use algebraic manipulation to prove that\[(A+C) \cdot(\bar{A}+B) \cdot(B+C)=B \cdot C\]
Find the complement of the following expressions:(a) \(A \bar{B}+\bar{A} B\)(b) \((\bar{V} W+X) Y+\bar{Z}\)(c) \(W X(\bar{Y} Z+Y \bar{Z})+\bar{W} \bar{X}(\bar{Y}+Z)(Y+\bar{Z})\)(d)
Optimize the following Boolean functions \(F\) together with the don't-care conditions \(d\) :(a) \(F(A, B, C, D)=\Sigma m(0,1,7,13,15), d(A, B, C, D)=\Sigma m(2,6,8,9,10)\)(b) \(F(W, X, Y, Z)=\Sigma
Illustrate the expansion or reduction performed on each implicant on a Kmap if the operation changes the implicant.(a) Apply the Espresso EXPAND routine to the following function.\[F(A, B, C,
+Apply the simplified Espresso algorithm to the following function. Show a K-map for each algorithm routine that changes one or more implicants.\[F(A, B, C, D)=\bar{A} \bar{B} \bar{D}+\bar{B} \bar{C}
Use decomposition to find minimum gate-input cost, multiple-level implementations for the functions given, using AND and OR gates and inverters.(a) \(F(A, B, C, D)=A \bar{B} C+\bar{A} B C+A \bar{B}
Use extraction to find a shared, minimum gate-input cost, multiple-level implementation for the pair of functions given, using AND and OR gates and inverters.(a) \(F(A, B, C, D)=\Sigma
Use elimination to flatten each of the function sets given into a two-level sumof-products form.(a) \(F(A, B, G, H)=A B \bar{G}+\bar{B} G+\bar{A} \bar{H}, G(C, D)=C \bar{D}+\bar{C} D\), \(H(B, C,
(a) Connect the outputs of three 3 -state buffers together, and add additional logic to implement the function\[F=\bar{A} B C+A B D+A \bar{B} \bar{D}\]Assume that \(C, D\), and \(\bar{D}\) are data
Design an excess-3-to-BCD code converter that gives output code 0000 for all invalid input combinations.
In Figure 10, simulation results are given for the BCD-to-excess-3 code converter for the BCD inputs for 0 through 9. Perform a similar logic simulation to determine the results for BCD inputs 10
Solve Problem 47 using two 3 -to-8-line decoders with enables, an inverter, and OR gates with a maximum fan-in of 4 .Data From Problem 47 47. *Implement the Boolean function F(A,B,C,D) = m(1,3,4, 11,
Compile and simulate the 2-to-4-line decoder with enable in Figure 12 for sequence \(000,001,010,011,100,101,110,111\) on E_n, A0, A1. Verify that the circuit functions as a decoder. You will need to
Compile and simulate the 2-to-4-line decoder Verilog description in Figure 20 for sequence 000, 001, 010, 011, 100, 101, 110, 111 on E, A0, A1. Verify that the circuit functions as a decoder.Data
Rewrite the Verilog description given in Figure 20 for the 2-to-4-line decoder using vector notation for inputs, outputs, and wires. See Figure 21 and accompanying text for these concepts. Compile
Compile and simulate the 4-to-1-line multiplexer in Figure 21 for the sequence of all 16 combinations of \(00,10,01,11\) on \(S\) and \(1000,0100,0010\), 0001 on D. Verify that the circuit functions
Find a function to detect an error in the representation of a decimal digit in BCD. In other words, write an equation with value 1 when the inputs are any one of the six unused bit combinations in
A trafic light control at a simple intersection uses a binary counter to produce the following sequence of combinations on lines A, B, C, and D: 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100,
Design a combinational circuit that accepts a 3-bit number and generates a 6-bit binary number output equal to the square of the input number.
Design a circuit with a 4-bit BCD input A, B, C, D that produces an output W, X, Y, Z that is equal to the input + 3 in binary. For example, 9 (1001) + 3 (0011) = 12 (1100). The outputs for invalid
A trafic metering system for controlling the release of trafic from an entrance ramp onto a superhighway has the following speciications for a part of its controller. There are three parallel
Design a circuit to implement the following pair of Boolean equations:To simplify drawing the schematic, the circuit is to use a hierarchy based on the factoring shown in the equation. Three
A hierarchical component with the function is to be used along with inverters to implement the following equation:The overall circuit can be obtained by using Shannon’s expansion theorem,where
Perform technology mapping to NAND gates for the circuit in Figure 3-54. Use cell types selected from: Inverter (n = 1), 2NAND, 3NAND, and 4NAND, as deined at the beginning of Section 3-2.Figure
Repeat Problem 3-16, using NOR gate cell types selected from: Inverter (n = 1), 2NOR, 3NOR, and 4NOR, each deined in the same manner as the corresponding four NAND cell types at the beginning of
(a) Repeat Problem 3-16 for the Boolean equations for the segments a and c of the BCD to seven-segment decoder from Example 3-18. Share common terms where possible.(b) Repeat part (a) using only
(a) Repeat Problem 3-18, mapping to NOR gate cell types as in Problem 3-17.Share common terms where possible.(b) Repeat part (a) using only Inverter (n = 1) and 2NOR cell types.Problem
Do Problem 3-21 by using logic simulation to find the output waveforms of the circuit or a partial truth-table listing, rather than finding Boolean functions.Problem 3-21The logic diagram for a
A special 4–to–6-line decoder is to be designed. The input codes used are 000 through 101. For a given code applied, the output Di, with i equal to the decimal equivalent of the code, is 1 and
An electronic game uses an array of seven LEDs (light-emitting diodes) to display the results of a random roll of a die. A decoder is to be designed to illuminate the appropriate diodes for the
Obtain the 1s and 2s complements of the following unsigned binary numbers: 10011100, 10011101, 10101000, 00000000, and 10000000.
sequential circuit with two D lip- lops A and B, two inputs X and Y, and one output Z is speciied by the following input equations:(a) Draw the logic diagram of the circuit.(b) Derive the state
A sequential circuit for a luggage lock has ten pushbuttons labeled 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. Each pushbutton 0 through 9 produces a 1 on Xi, i = 0 through 9, respectively, with all other
A serial 2s complementer is to be designed. A binary integer of arbitrary length is presented to the serial 2s complementer, least signiicant bit irst, on input X. When a given bit is presented on
The sequence in Problem 4-21 is a lag used in a communication network that represents the beginning of a message. This lag must be unique. As a consequence, at most ive 1s in sequence may appear
In many communication and networking systems, the signal transmitted on the communication line uses a non- return- to- zero (NRZ) format. USB uses a speciic version referred to as non- return- to-
Repeat Problem 4-27 with D lip- lops using a Gray- code assignment.Problem 4-27:A sequential circuit has two lip- lops A and B, one input X, and one output Y. The state diagram is shown in Figure
Design the register address logic in the pipelined CISC CPU by using information given in the register ields of Table 10-4 plus multiple-bit multiplexers, AND gates, OR gates, and inverters.Table 10-4
A CPU produces the following sequence of read addresses in hexadecimal:54, 58, 104, 5C, 108, 60, F0, 64, 54, 58, 10C, 5C, 110, 60, F0, 64.Supposing that the cache is empty to begin with, and assuming
Repeat Problem 12-1 for the following sequence of read addresses: 0, 4, 12, 8, 14, 1C, 1A, 28, 26, 2E, 36, 30, 3E 38, 46, 40, 4E, 48, 56, 50, 5E, 58.Problem 12-1A CPU produces the following sequence
A computer has a 32-bit address and a direct-mapped cache. Addressing is to the byte level. The cache has a capacity of 1 KB and uses lines that are 32 bytes. It uses write-through and so does not
A two-way set-associative cache in a system with 32-bit addresses has four 4-byte words per line and a capacity of 1 MB. Addressing is to the byte level.(a) How many bits are there in the index and
Discuss the advantages and disadvantages of:(a) Instruction and data caches versus a unified cache for both.(b) Write-back cache versus a write-through cache.
Give an example of a sequence of program and data memory read addresses that will have a high hit rate for separate instruction and data caches and a low hit rate for a unified cache. Assume
Give an example of a sequence of program and data memory read addresses that will have a high hit rate for a unified cache and a low hit rate for separate instruction and data caches. Assume that
Explain why write-allocate is typically not used in a write-through cache.
A 1 KB cache in a system with 32-bit addresses using byte addressing is organized using four 4-byte words per line and direct mapping.(a) How many sets are in the cache?(b) How many bits are in the
A high-speed workstation has 64-bit words and 64-bit addresses with address resolution to the byte level.(a) How many words can be in the address space of the workstation?(b) Assuming a
A cache memory has an access time from the CPU of 4 ns, and the main memory has an access time from the CPU of 40 ns. What is the effective access time for the cache–main memory hierarchy if the
Repeat Problem 12-11 if the cache access time from the CPU is 1 ns and the main memory has an access time from the CPU of 20 ns.Problem 12-11A cache memory has an access time from the CPU of 4 ns,
Redesign the cache in Figure 12-7 so that it is the same size, but is four-way set associative rather than two-way set associative.Figure 12-7 CPU CPU Hit/ miss Tag Index Address bus Tag Tag Data
The cache in Figure 12-9 is to be redesigned to use write-back with write allocate rather than write-through. Respond to the following requests, making sure to deal with all of the address and data
A virtual memory system uses 4 KB pages, 64-bit words, and a 48-bit virtual address. A particular program and its data require 4263 pages.(a) What is the minimum number of page tables
A computer uses 64-bit virtual addresses, 32-bit words, and a page size of 4 KB. The computer has 1 GB of physical memory.(a) How many bits of the address are used for the page offset?(b) How many
A small TLB has the following entries for a virtual page number of length 20 bits, a physical page number of 12 bits, and a page offset of 12 bits.The page numbers and offset are given in
A computer can accommodate a maximum of 384 MB of main memory. It has a 32-bit word and a 32-bit virtual address and uses 4 KB pages. The TLB contains only entries that include the Valid, Dirty, and
Four programs are concurrently executing in a multitasking computer with virtual memory pages having 4 KB. Each page table entry is 32 bits. What is the minimum numbers of bytes of main memory
In caches, we use both write-through and write-back as potential writing approaches. But for virtual memory, only an approach that resembles writeback is used. Give a sound explanation of why this is
Explain clearly why both the cache memory concept and the virtual memory concept would be ineffective if locality of reference of memory-addressing patterns did not hold.
By using manual methods, verify that the circuit of Figure 3-55 generates the exclusive-NOR function.Figure 3-55 X Y Do -F
(a) Use logic simulation to verify that the circuits described in Example 3-18 implement the BCD–to–seven-segment converter correctly.(b) Design the converter assuming that the unused input
Complete the design of the BCD–to–seven-segment decoder by performing the following steps:(a) Plot the seven maps for each of the outputs for the BCD–to–sevensegment decoder speciied in
Repeat Problem 3-4 for 4 x 4 tic-tac-toe, which is played on a four-by-four grid. Assume that the numbering pattern is left to right and top to bottom, as in Problem 3-4.Problem 3-4A simple
A simple well-known game, tic-tac-toe, is played on a three-by-three grid of squares by two players. The players alternate turns. Each player chooses a square and places a mark in a square. (One
A majority function has an output value of 1 if there are more 1s than 0s on its inputs. The output is 0 otherwise. Design a three-input majority function.
A home security system has a master switch that is used to enable an alarm, lights, video cameras, and a call to local police in the event one or more of six sets of sensors detects an intrusion. In
Design a Gray code–to–BCD code converter that gives output code 1111 for all invalid input combinations. Assume that the Gray code sequence for decimal numbers 0 through 9 is 0000, 0001, 0011,
A low-voltage lighting system is to use a binary logic control for a particular light. This light lies at the intersection point of a T-shaped hallway. There is a switch for this light at each of the
Design a combinational circuit that accepts a 4-bit number and generates a 3-bit binary number output that approximates the square root of the number. For example, if the square root is 3.5 or
The logic diagram for a 74HC138 MSI CMOS circuit is given in Figure 3-56. Find the Boolean function for each of the outputs. Describe the circuit function carefully.Figure 3-56 A B C- G GA GB 8 8 -
A NAND gate with eight inputs is required. For each of the following cases, minimize the number of gates used in the multiple-level result:(a) Design the 8-input NAND gate using 2-input NAND gates
(a) Draw an implementation diagram for a constant vector function F = (F7, F6, F5, F4, F3, F2, F1, F0) = (1, 0, 0, 1, 0, 1, 1, 0) using the ground and power symbols in Figure 3-7(b).(b) Draw an
Design a 4–to–16-line decoder with enable using ive 2–to–4-line decoders with enable as shown in Figure 3-16.Figure 3-16. EN A Ao 0 X X 1 0 1 1 1 1 00x 1 0 1 1 Do D D D3 0 0 0 0 0 0 1 0 0 0 1
(a) Draw an implementation diagram for rudimentary vector function (b) and the wire and inverter in Figures 3-7 (c) and (d).Figure 3-7 F = (F7, F6,F5, F4, F3, F2, F1, F0) = (A,A,1,A,A,0,1,A),
To provide uphill running and walking, an exercise treadmill has a grade feature that can be set from 0.0% to 15.0% in increments of 0.1%. (The grade in percent is the slope expressed as a
(a) Draw an implementation diagram for the vector G = (G5 , G4 , G3 , G2 , G1, G0) = (F13, F8, F5, F3, F2, F1).(b) Draw a simple implementation for the rudimentary vector H = (H7, H6, H5, H4, H3,
Design a 4–to–16-line decoder using two 3–to–8-line decoders and 16 2-input AND gates.
Design a 5–to–32-line decoder using a 3–to–8-line decoder, a 2–to–4-line decoder, and 32 2-input AND gates.
Draw the detailed logic diagram of a 3–to–8-line decoder using only NOR and NOT gates. Include an enable input.
Design a 4-input priority encoder with inputs and outputs as in Table 3-6, but with the truth table representing the case in which input D0 has the highest priority and input D3 the lowest
Derive the truth table of a decimal-to-binary priority encoder. There are 10 inputs I1 through I9 and outputs A3 through A0 and V. Input I9 has the highest priority.
(a) Design an 8–to–1-line multiplexer using a 3–to–8-line decoder and an 8 х 2 AND-OR.(b) Repeat part (a), using two 4–to–1-line multiplexers and one 2-to-1-line multiplexer.
Design a 16–to–1-line multiplexer using a 4–to–16-line decoder and a 16 х 2 AND-OR.
Design a dual 8–to–1-line decoder using a 3–to–8-line decoder and two 8 х 2 AND-ORs.
Rearrange the condensed truth table for the circuit of Figure 3-16, and verify that the circuit can function as a demultiplexer.Figure 3-16 EN A Ao Do D D D3 0 X X 0 0 0 1 0 1 0 0 1 1 1 1 1 0 1 0 1 0
Construct a 12–to–1-line multiplexer with a 3–to–8-line decoder, a 1–to–2- line decoder, and a 12 х 3 AND-OR. The selection codes 0000 through 1011 must be directly applied to the
The rear lights of a car are to be controlled by digital logic. There is a single lamp in each of the rear lights.(a) Write the equations for LR and RR. Assume that BR overrides EM and that LT and
Construct a quad 10–to–1-line multiplexer with four single 8–to–1-line multiplexers and two quadruple 2–to–1-line multiplexers. The multiplexers should be interconnected and inputs
Construct a 15–to–1-line multiplexer with two 8–to–1-line multiplexers. Interconnect the two multiplexers and label the inputs such that any added logic required to have selection codes 0000

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