Rewrite the Verilog description given in Figure 20 for the 2-to-4-line decoder using vector notation for inputs, outputs, and wires. See Figure 21 and accompanying text for these concepts. Compile and simulate the resulting file as in Problem 31.

Data From Figure 21

Data From Figure 20

Data From Problem 31

Transcribed Image Text:

EN A Ao Do D1 D2 D3 0 X X 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 (a) EN A1 Ao -Do D D2 D D3 (b) FIGURE 21 A 2-to-4-Line Decoder with Enable