Do a manual verification of the solution (either yours or the one posted on the text website) to Problem 27. Consider all transitions where \(S\) and \(R\) change with the clock equal to 0.

Data From Problem 27

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27. *A set-dominant master-slave flip-flop has set and reset inputs. It differs from a conventional master-slave SR flip-flop in that, when both S and R are equal to 1, the flip-flop is set. (a) Obtain the state table of the set-dominant flip-flop. (b) Find the state diagram for the set-dominant flip-flop. (c) Design the set-dominant flip-flop by using an SR flip-flop and logic gates (including inverters).