A set-dominant master-slave flip-flop has set and reset inputs. It differs from a conventional master-slave \(S R\) flip-flop in that, when both \(S\) and \(R\) are equal to 1 , the flip-flop is set.

(a) Obtain the state table of the set-dominant flip-flop.

(b) Find the state diagram for the set-dominant flip-flop.

(c) Design the set-dominant flip-flop by using an \(S R\) flip-flop and logic gates (including inverters).