Obtain a timing diagram similar to Figure 10 for a positive-edge-triggered \(J K\) flip-flop during four clock pulses. Show the timing signals for \(C, J, K, Y\), and \(Q\). Assume that initially the output \(Q\) is equal to 1 , with \(J=0\) and \(K=1\) for the first pulse. Then, for successive pulses, \(J\) goes to 1 , followed by \(K\) going to 0 and then \(J\) going back to 0 . Assume that each input changes near the negative edge of the pulse.

Data From Figure 10

Transcribed Image Text:

cr Y Q 0 1 I 1 50 ns 100 ns 150 ns 200 ns FIGURE 10 Logic Simulation of an SR Master-Slave Flip-Flop