Exercise 8.8 (Verification of the Realizability of a Finite-State Machine Specified by a Sequential Circuit). Analyze the realizability of several finite-state machines. Detailed information about the finite-state machines to be analyzed are given in Exercises 8.7. Practical tasks:

1 Load the final TVL system of Exercise 8.5.

2 Verify whether the system function of object number 7 is realizable.

3 Verify that all memory functions sfi(x1, x2, s1.s2, s3), i = 1, 2, 3 are uniquely specified by the system equation F(x, s, sf , y) = 1.

4 Verify that all result functions yj(x1, x2, s1.s2, s3), j = 1, 2 are uniquely specified by the system equation F(x, s, sf , y) = 1.