(a) Calculate the delay, in terms of logic gate delays, for the product bit p7 in each of the arrays in Figure 6.16. Assume that each output from a full adder is available two gate delays after the inputs are available. Include the AND gate delay to generate all miq; products at the beginning.

(b) The delay for the extension of Figure 6.16a to the n x n case has been stated as 6(n-1)-1 in Section 6.4. Develop a similar expression for the extension of Figure 6.166 to the n x n case.

LO1