Assume that in the bus arbitration arrangement in Figure 4.20, the processor keeps asserting BG1 as long as BR is asserted. When device i is requesting the bus, it becomes the bus master only when it receives a low-to-high transition on its BGi input.

(a) Assume that devices are allowed to assert the BR signal at any time. Give a sequence of events to show that the system can enter a deadlock situation, in which one or more devices are requesting the bus, the bus is free, and no device can become the bus master.

(b) Suggest a rule for the devices to observe in order to prevent this deadlock situation from occurring.