00 00 1) A state transition diagram for a synchronous finite state machine is shown in Figure 3. Derive the combinatorial logic required to implement this FSM with the use of Karnaugh maps. Note that any transitions which are not shown in the diagram may be treated as "don't care". Is this a Mealy or a Moore machine? Why? 00 00 A/O 01 B/0 10 01 10 C/O 10 D/1 01 Any input 2) A serial multiplier circuit is constructed from a binary adder and registers to produce an 8-bit unsigned product from two 4bit input words. Show the contents of the registers step by step when the multiplier is used to multiply 14 by 11. Explain and discuss any reasons for using serial multipliers in preference to parallel multipliers. Explain and discuss any reasons for using parallel multipliers to serial multipliers. 00