The Verilog code in Figure P5.11 is equivalent to the code in Figure P5.9, except that blocking assignments are used. Draw the circuit represented by this code. What is its counting sequence?

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module Ifsr (R, L, Clock, Q); input [0:2] R; input L, Clock; output reg [0:2] Q: always @(posedge Clock) if (L) Q<= R; else begin Q[0] = Q[2]; Q[1] = Q[0] ^ Q[2]; Q[2] = Q[¹]; end endmodule