0110011 0000011 0100011 1100011 R-typ be RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOpt Problem 2 (25 points) Consider a pipeline architecture with perfect branch prediction (no stalls), with no delay slots, which has full forwarding support and which resolves branches in the EX (not ID) stage. This pipeline executes the code below THERE ld x25, 0 (x26) add x22, x26, x27 subi x28, x22, 8 bne x28, x0, THERE Kafter 1> Kafter 4> a) Comment the code to indicate what each instruction does; also indicate if/when there are dependency, and/or control hazards b) Draw the pipeline graphical representation when it executes two iterations of the loop above Assume cc1 is when THERE 1d x25.... instruction is first fetched c) For question b) which are the clock cycles for which the pipeline is full? d) Are there pipeline stages that just let partial results migrate from one pipeline register to the next but do nothing with them? 0110011 0000011 0100011 1100011 R-typ be RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOpt Problem 2 (25 points) Consider a pipeline architecture with perfect branch prediction (no stalls), with no delay slots, which has full forwarding support and which resolves branches in the EX (not ID) stage. This pipeline executes the code below THERE ld x25, 0 (x26) add x22, x26, x27 subi x28, x22, 8 bne x28, x0, THERE Kafter 1> Kafter 4> a) Comment the code to indicate what each instruction does; also indicate if/when there are dependency, and/or control hazards b) Draw the pipeline graphical representation when it executes two iterations of the loop above Assume cc1 is when THERE 1d x25.... instruction is first fetched c) For question b) which are the clock cycles for which the pipeline is full? d) Are there pipeline stages that just let partial results migrate from one pipeline register to the next but do nothing with them