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BIRZEIT UNIVERSITY

Faculty of Engineering and Technology Electrical and Computer Engineering Department Digital Systems ENCS$2340$ Verilog HDL Project

Project title: Design and Implementation of a Simple ALU using Verilog HDL Due date: Tuesday, January ${23}^{rd},2024$

This project is to be done individually.

You need to submit your codes.

Write a report for your results by providing the code and the simulation results of every component as well as the whole system.

NOTE:

The grading of the project will be via discussion.

This project should be implemented in Verilog HOL using Quartus software

DO NOT:

Give$/$receive code or proofs to$/$from other students

DO:

Meet with other students to discuss the project fit is best not to take any notes during such meetings, and to re$-$work project on your own$)$

Use online resources $($e$.$g$.$ Wikipedia$)$ to understand the concepts needed to solve the project

Project Description:

In this project, you will design a simple Arithmetic Logic Unit $($ALU$)$ using Verilog Hardware Description Language $($HDL$).$ The ALU should be capable of performing four basic arithmetic and logic operations: addition, subtraction, bitwise AND, and bitwise OR$.$

Objective:

To develop a comprehensive understanding of Verilog HDL for hardware description.

To design and implement a simple ALU with four basic functionalities.

To explore structural, dataflow, and behavioral modeling techniques in Verilog. Tasks:

ALU Design:

Define inputs and outputs of the ALU.

Select four essential arithmetic and logical operations to implement $($e$.$g$.,$ addition, subtraction, AND, OR$).$

Create a block diagram representing the ALU's structure.

Verilog Modules: