1. (16 pts) Suppose we have the following cache (note that it is a word-addressable machine): Sete Tag L3:WIL3:WO Tag L2:WI L2-WOTag LI-WILI-WOTag LO:WILO:WO 00011 Al AO 0001 KIKO omul MIMO 110 BIBO 00011 NINO 110 PIPO 2 131110 cic0 101 DIDO 4 11101 ElEO 1010 0100 1011 RI RO on FIFO 5 6 0100 HI HO 1010 SI S OONI TI TO 010 20 7 0001 GIGO 0101 UI UO 0011 VIVO 1001 YI YO The columns labeled Li:Wi contain the jth data word for line Li (e... LI:WO contains the Of word in the 1" line). The cache policies are: Replacement: random Write allocate: bypass-cache (i.e., no-allocate). Write update: write-through. (a) [4 pts) What is the address of the following data words found in the cache above? Data word Address Q1 SO M0 Y1 (b) 7 pts) Suppose the addresses in the following trace are accessed in order, possibly changing the cache on cach access. The R/W column indicates whether the access was a read or a write access. For each access, determine (1) which set in the cache would be accessed to look for the addressed data, (2) does the cache access for this address access result in a hit or a miss? (3) if there is a miss, what type of miss is it? Assume that if the addresses do not appear in the cache above, the addresses have not been accessed before the start of this trace. Be sure your answer is consistent with the cache's policies, listed above. R/W Address Set # Hit/Miss? Conflict Miss? Capacity Miss? Compulsory Miss? Read 11100110 Write 11110011 Read 11110010 Write 11110011 Read 00000010 (c) [2 points] What is the size of the physical (main) memory in words? (d) [3 points) Suppose the cache access time is 10ns and main memory access time is 50ns/word. What is the maximum number of misses out of 1000 total accesses that this cache memory system can have before it exceeds an effective access time of 20ns? 1. (16 pts) Suppose we have the following cache (note that it is a word-addressable machine): Sete Tag L3:WIL3:WO Tag L2:WI L2-WOTag LI-WILI-WOTag LO:WILO:WO 00011 Al AO 0001 KIKO omul MIMO 110 BIBO 00011 NINO 110 PIPO 2 131110 cic0 101 DIDO 4 11101 ElEO 1010 0100 1011 RI RO on FIFO 5 6 0100 HI HO 1010 SI S OONI TI TO 010 20 7 0001 GIGO 0101 UI UO 0011 VIVO 1001 YI YO The columns labeled Li:Wi contain the jth data word for line Li (e... LI:WO contains the Of word in the 1" line). The cache policies are: Replacement: random Write allocate: bypass-cache (i.e., no-allocate). Write update: write-through. (a) [4 pts) What is the address of the following data words found in the cache above? Data word Address Q1 SO M0 Y1 (b) 7 pts) Suppose the addresses in the following trace are accessed in order, possibly changing the cache on cach access. The R/W column indicates whether the access was a read or a write access. For each access, determine (1) which set in the cache would be accessed to look for the addressed data, (2) does the cache access for this address access result in a hit or a miss? (3) if there is a miss, what type of miss is it? Assume that if the addresses do not appear in the cache above, the addresses have not been accessed before the start of this trace. Be sure your answer is consistent with the cache's policies, listed above. R/W Address Set # Hit/Miss? Conflict Miss? Capacity Miss? Compulsory Miss? Read 11100110 Write 11110011 Read 11110010 Write 11110011 Read 00000010 (c) [2 points] What is the size of the physical (main) memory in words? (d) [3 points) Suppose the cache access time is 10ns and main memory access time is 50ns/word. What is the maximum number of misses out of 1000 total accesses that this cache memory system can have before it exceeds an effective access time of 20ns
