1. (16 pts) Suppose we have the following cache (note that it is a word-addressable machine): Seti Tag L3:W1 L3-Wo Tag L2-W1 L2:WO Tag LI:WILI:Wo Tag LO:WILO:WO 0 00111 AL AO 0001 KITKO ou MIMO 1 1101 BIBO 00:01 NINO 1110 PIPO 2 31110 CIC 1101 | DIDO 4 1110 ElE01010 0100 101 RI RO oul FIFO 6 7 0100 0001 HI HO GIGO 1010 0101 SI UI SO UO ou 0011 TI TO VIVO 0101 1001 Ji YI JO YO word in the 1" The columns labeled Li:Wi contain the jth data word for line Li (e... L1:WO contains the line). The cache policies are: Replacement: random Write allocate: bypass-cache (i.e., no-allocate). Write update: write-through. (a) (4 pts) What is the address of the following data words found in the cache above? Address Data word Q1 SO 0 Y1 (b) [7 pts) Suppose the addresses in the following trace are accessed in order, possibly changing the cache on each access. The R/W column indicates whether the access was a read or a write access. For each access, determine (1) which set in the cache would be accessed to look for the addressed data, (2) does the cache access for this address access result in a hit or a miss? (3) if there is a miss, what type of miss is it? Assume that if the addresses do not appear in the cache above, the addresses have not been accessed before the start of this trace. Be sure your answer is consistent with the cache's policies, listed above. Set # Hit/Miss? Conflict Miss? Capacity Miss? Compulsory Miss RW Read Address 11100110 Write 11110011 Read 11110010 Write 11110011 Read 00000010 (c) [2 points) What is the size of the physical (main) memory in words? (d) (3 points Suppose the cache access time is 10ns and main memory access time is 50ns/word. What is the maximum number of misses out of 1000 total accesses that this cache memory system can have before it exceeds an effective access time of 20ns? 1. (16 pts) Suppose we have the following cache (note that it is a word-addressable machine): Seti Tag L3:W1 L3-Wo Tag L2-W1 L2:WO Tag LI:WILI:Wo Tag LO:WILO:WO 0 00111 AL AO 0001 KITKO ou MIMO 1 1101 BIBO 00:01 NINO 1110 PIPO 2 31110 CIC 1101 | DIDO 4 1110 ElE01010 0100 101 RI RO oul FIFO 6 7 0100 0001 HI HO GIGO 1010 0101 SI UI SO UO ou 0011 TI TO VIVO 0101 1001 Ji YI JO YO word in the 1" The columns labeled Li:Wi contain the jth data word for line Li (e... L1:WO contains the line). The cache policies are: Replacement: random Write allocate: bypass-cache (i.e., no-allocate). Write update: write-through. (a) (4 pts) What is the address of the following data words found in the cache above? Address Data word Q1 SO 0 Y1 (b) [7 pts) Suppose the addresses in the following trace are accessed in order, possibly changing the cache on each access. The R/W column indicates whether the access was a read or a write access. For each access, determine (1) which set in the cache would be accessed to look for the addressed data, (2) does the cache access for this address access result in a hit or a miss? (3) if there is a miss, what type of miss is it? Assume that if the addresses do not appear in the cache above, the addresses have not been accessed before the start of this trace. Be sure your answer is consistent with the cache's policies, listed above. Set # Hit/Miss? Conflict Miss? Capacity Miss? Compulsory Miss RW Read Address 11100110 Write 11110011 Read 11110010 Write 11110011 Read 00000010 (c) [2 points) What is the size of the physical (main) memory in words? (d) (3 points Suppose the cache access time is 10ns and main memory access time is 50ns/word. What is the maximum number of misses out of 1000 total accesses that this cache memory system can have before it exceeds an effective access time of 20ns
