$13\mathrm{.}3$ Typically, at the completion of a device I$/0,$ a single interrupt is raised and appropriately handled by the host processor. In certain settings, however, the code that is to be executed at the completion of the I$/0$ can be broken into two separate pieces. The first piece executes immediately after the I$/0$ completes and schedules a second interrupt for the remaining piece of code to be executed at a later time. What is the purpose of using this strategy in the design of interrupt handlers?