1. (30) For the following, assume you are given code for a full adder entity and architecture: entity full_add is port( A, B, Cin : in std logic; Cout, s out std_logic); end entity; a. You are implementing structural VHDL code for a 4-bit magnitude comparator that is required to include a 4-bit subtractor, built from the full add" entity shown above. Assume your entity port list includes 2 4-bit inputs (A and B) and a 2-bit output indicating greater than, less than or equal. How might the carry output bit and 4 sum bits from the 4-bit subtractor be used to implement your magnitude comparator? b. Draw a schematic of the top level architecture as you desire it to be synthesized. You only need to show the "black box view of any "full add" instances. c. For the 4-bit structural comparator described above, write code using the 'generate' statement for only the body (between 'begin' and 'end') of the architecture implementing this module. Note any internal signals that need to be declared. 1. (30) For the following, assume you are given code for a full adder entity and architecture: entity full_add is port( A, B, Cin : in std logic; Cout, s out std_logic); end entity; a. You are implementing structural VHDL code for a 4-bit magnitude comparator that is required to include a 4-bit subtractor, built from the full add" entity shown above. Assume your entity port list includes 2 4-bit inputs (A and B) and a 2-bit output indicating greater than, less than or equal. How might the carry output bit and 4 sum bits from the 4-bit subtractor be used to implement your magnitude comparator? b. Draw a schematic of the top level architecture as you desire it to be synthesized. You only need to show the "black box view of any "full add" instances. c. For the 4-bit structural comparator described above, write code using the 'generate' statement for only the body (between 'begin' and 'end') of the architecture implementing this module. Note any internal signals that need to be declared