1. [50] points] Attached is a thesis by Suijkerbuijk. We have discussed multithreaded and pipelined architectures. As you address the questions posed below, list which references, not including the course textbook, that you found to aid in your understanding of the issues. These references may include references given in the textbook or in the thesis; however, if you reference a paper, at least read the relevant section that assisted your work.

1.1. In the conclusions of the thesis, the author states: The architecture we propose is one purely based on hardware implementation, but for better performance we need software enhancements. These software enhancements can force a thread switch when that is required in stead of waiting for the QTE to do a forced switch. We used three benchmark programs to determine the performance of the multithreaded TriMedia. The first program showed the benefits of the shared cache. But it was not a real application. The second program was a manually optimized 1 mpegdecoder. This program showed that improvement with a multithreaded architecture is not as self evident as it may seem. The optimized program had a benefit, but not that much and only with a certain QTE. The third program was an unoptimized mpegdecoder. The results for this benchmark were a great improvement compared to the optimized mpegde- coder. It showed a significant increase of around 25%. This improvement is achieved with two hardware threads. We noticed that adding a second bus interface will give a better performance and at a relative smaller cost. The two threaded TriMedia with two bus interfaces does give significant speedup at relative small chip size increase of about 21%.

1.1.1. How would you explain that the addition of a second bus interface would give better performance?

1.1.2. The author states that for better performance, we need software enhancements. In the body of the thesis, this idea is explained, primarily through a compiler that would not need the QTE forced by the author.

1.1.2.1. Define QTE as explained by the thesis author. (Note that this has nothing to do with quantum computing.)

1.1.2.2. The author proposes a compiler that would have enhancements that would not require a QTE. Is there anyway to do this without either a hardware or software timer that verifies an infinite loop, or to use a stall? Why must such a timer be in an "end-user" mode of execution (not "supervisor" mode)? (Hint: consider the cost of a context switch.)