1. A CPU has 5 bits physical address and generates addresses 00, 01, 08, 09,19 18,06, OE, OF and 16 in hex. A. Show the contents of the cache using two way set associative mapping, assume LRU replacement policy. B. What is hit rate? Main memory Address Content 000005 Cache memory 00001 3 00010 11 00011 6 001007 v Tag Date LRU Tag Data LAU 00101 8 001109 00111 12 010000 01001 o 010108 01011 7 011009 01101 o 011102 01111 s Address Content 100005 100010 10010 1 10011 11 10100 15 10101 09 10110 12 10111 23 11000 65 11001 21 11010 8 110117 111009 111010 111102 111115