1. A machine is called underpipelined if additional levels of pipelining can be added without changing the pipeline stall behavior appreciably. Suppose that the MIPS integer pipeline was changed to four stages by merging EX and MEM stages and lengthening the clock cycle time by 50%. How much faster would the conventional MIPS pipeline be versus the underpipelined MIPS on integer codes only? Assume that the branch is resolved in the ID stage and forwardings are available. Make sure that you include the effect of any changes in pipeline stalls for load and branch instructions using the following data: load instructions ----10% branch instructions -- 6%