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1 . Assume that a direct - mapped cache has: four 4 - byte cache blocks ( lines ) ; 6 - bit memory addresses;

1. Assume that a direct-mapped cache has:
four 4-byte cache blocks (lines);
6-bit memory addresses;
write-back and write-allocate policy;
memory-byte addressable; and
big Endian byte-ordering schemes.
Assume that all accesses are to READ or WRITE a single byte. The initial conditions of the data
cache memory and a part of memory are:
i. Cache memory (initial condition):
Index # Valid Dirty Tag Data (in hex)
001000 A1 A2 A3 A4
011001 C5 C6 C7 C8
101000 B1 B2 B3 B4
111001 D5 D6 D7 D8
ii. A part of Memory (initial condition):
Address Contents (in hex) Address Contents (in hex)
000000 A1 A2 A3 A4011000 D1 D2 D3 D4
000100 A5 A6 A7 A8011100 D5 D6 D7 D8
001000 B1 B2 B3 B4100000 E1 E2 E3 E4
001100 B5 B6 B7 B8100100 E5 E6 E7 E8
010000 C1 C2 C3 C4101000 F1 F2 F3 F4
010100 C5 C6 C7 C8101100 F5 F6 F7 F8
iii. The processor of a load/store machine fetched and executes according to the following
sequence of memory addresses (memory references, from 1 to 6). Assume 11,22, and 33
are hex values.
Order Memory reference Inst. Type Description
1010001 load
2000101 Load
301000111 Store Write 11 to 010001
400010122 Store Write 22 to 000101
5100000 Load
610010033 Store Write 33 to 100100
a) Which of the memory references (from 1 to 6) will be misses? You can list the memory
references by using 1 to 6.
b) After execution of memory references from 1 to 6, show the updated contents of the cache
memory. You can answer the changes only but do show the entire cache line.
Index # Valid Dirty Tag Data (in hex)
00
01
10
11
c) Are there any updates in the contents of memory after execution of memory references from
1 to 6? If yes, show the updated memory contents. You can answer the changes only.
Address Contents (in hex) Address Contents (in hex)
000000011000
000100011100
001000100000
001100100100
010000101000
010100101100

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