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1 . Assume that a direct - mapped cache has: four 4 - byte cache blocks ( lines ) ; 6 - bit memory addresses;
Assume that a directmapped cache has:
four byte cache blocks lines;
bit memory addresses;
writeback and writeallocate policy;
memorybyte addressable; and
big Endian byteordering schemes.
Assume that all accesses are to READ or WRITE a single byte. The initial conditions of the data
cache memory and a part of memory are:
i Cache memory initial condition:
Index # Valid Dirty Tag Data in hex
A A A A
C C C C
B B B B
D D D D
ii A part of Memory initial condition:
Address Contents in hex Address Contents in hex
A A A A D D D D
A A A A D D D D
B B B B E E E E
B B B B E E E E
C C C C F F F F
C C C C F F F F
iii. The processor of a loadstore machine fetched and executes according to the following
sequence of memory addresses memory references, from to Assume and
are hex values.
Order Memory reference Inst. Type Description
load
Load
Store Write to
Store Write to
Load
Store Write to
a Which of the memory references from to will be misses? You can list the memory
references by using to
b After execution of memory references from to show the updated contents of the cache
memory. You can answer the changes only but do show the entire cache line.
Index # Valid Dirty Tag Data in hex
c Are there any updates in the contents of memory after execution of memory references from
to If yes, show the updated memory contents. You can answer the changes only.
Address Contents in hex Address Contents in hex
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