1. Assume the following table for the problem. Type of Instruction ALU Memory Branch Latency (cycles) 1 100 2 Frequency (%) 30 40 30 You would like to introduce a cache that returns the data value in 10 cycles. But, if there is a cache miss, total access latency will increase to 10+100=110 cycles due to sequential nature of the memory access. What is the effect of introducing a cache that gives 50% hit rate on performance? Show your work using the execution time formula.