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(1). Computer C's performance is 4 times as fast as the performance of computer B, which runs a given application in 28 seconds. How long

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(1). Computer C's performance is 4 times as fast as the performance of computer B, which runs a given application in 28 seconds. How long will computer C take to run that application? (a) 7 seconds (b) 14 seconds (c) 56 seconds (d) 112 seconds (2). MIPS is kind of language. (a) high-level (b) assembly (c) machine (d) Java (3). What's the decimal value of (10001111)2 ? (a) 208 (b) 79 (c) 195 (d) 203 (4). Given a register $t1, how to set its four least-significant bits as 0 s ? (a) and \$t0, \$t1, 0x0FFFFFFF (b) sub \$t0, \$t1, 0x0FFFFFFF (c) and $t0,$t1,0xFFFFFFF0 (d) sub \$t0, \$t1, 0xFFFFFFF0 (5). What's the binary value of (b19e) hex? (a) 1010000111001001 (b) 1110000110011110 (c) 1011000110011110 (d) 1011000110101010 (6). How many bits are assigned for 'shamt' field in a MIPS R-type instruction. (a) 5 (b) 6 (c) 7 (d) 8 (7). For 2's-complement signed integers, which one is the most negative? (a) 10000000.0000 (b) 111111111111 (c) 011111111111 (d) 000000000000 (8). Scheduling and speculation via , both in hardware and in software, are the primary techniques used to reduce the performance impact of dependences. (a) subtraction (b) parallelism (c) pipelining (d) prediction (9). Many microprocessors use hardware to try to predict accesses that may be difficult for software to notice. (a) prefetching (b) cache (c) prediction (d) reorganization (10). As processors operating in parallel will normally share data, they also need to consider when operating on shared data. (a) multicore (b) multiprocessors (c) synchronization (d) cache coherence 2. Fill in Questions ( 10 Points, Each Blank 1 point) (1). is used to represent the design at different levels of representation; lower-level details are hidden to offer a simpler model at higher level. (2). According to Moore's Law, integrated circuit resources double every months. (3). The power required per transistor depends on (4). Computer memory hierarchy consists of different components: (5). is an implementation technique in which multiple instructions are overlapped in execution

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