$$ 1. Consider a CMOS gate with the following logic expression: Y=\overline{A \cdot B+C) $$ a) Sketch a transistor-level schematic. [4] b) Sketch a stick diagram. [4] c) Estimate the width, height and area from the stick diagram, for a $32 \mathrm{-nm} $ process. [2] CS.JG.021