1) Consider a system with memory mapping done on a page basis and using a single level page table. Assume that that necessary page table is always in memory.

1. If a memory reference takes 200 ns, how long a paged memory reference takes?
2. If there are 2 level page tables, what is the time now?
3. Now we add, MMU that imposes an overhead of 20ns on a hit or a miss. If we have 85% hit ratio, what would be EAT?

Q2. A paging system uses 16-bit address and 4K pages. Shown are the two page tables for the two processes

Complete the following table with the given information

Process	Adress	Page #	Offset	Physical address
Process 1	11,034
Process 2	12,345

Q3. Suppose, on a machine with 16-bit virtual and physical addresses and a page size of 256 bytes, a process is running and the TLB contains the following:

1	32	4F
1	1A	C3
1	89	22
0	42	B2

where, from left to right, the columns contain the valid bit, the virtual page number, and the page frame number. All numbers are given in hexadecimal. If the process issues the virtual address 1AF2 hex, what physical address (in hex) will the MMU issue? Show your work