1. Consider an nMOS transistor in a 0.6 m process with W/L= 1.2/0.6 (m/m). In this process the gate oxide thickness is 100 and the mobility of electrons is 350 cm/V-s. The threshold voltage is 0.7 V. Plot los versus Vos for VGs = 0, 1, 2, 3, 4 and 5 V. 2. A 90nm long transistor has a gate oxide thickness of 16 . What is it gate capacitance per micron of width. 3. Consider the nMOS transistor in a 0.6 um process with gate oxide thickness of 100. The doping level is N = 2107 cm and the nominal threshold voltage is 0.7 V. The body is tied to ground with a substrate contact. How much the threshold voltage changes at room temperature if the source voltage is 4 V instead of 0 V. n = 1.45x100 cm. 4. An nMOS transistor has a threshold voltage of 0.4 V and a supply voltage of VDD = 1.2 V. A circuit designer is evaluating a proposal to reduce Vth by 100 mV to obtain a faster transistor. a) By what factor would the saturation current increases (at VGS-VDS-VDD), if the transistor were ideal. b) By what factor the subthreshold leakage current increase at room temperature at VGs=0? Assume n=1.4. c) By what factor would the subthreshold current increase at 120C? Assume threshold voltage independent of temperature. 5. Find the subthreshold leakage current of an inverter at room temperature if the input A=0. Let Bn=2Bp=1 mA/V, n=1.0, and Vtn=0.4V. Assume the body effect and DIBL coefficient are zero. 6. Consider an nFET process that uses an n-type poly gate. The important processing parameter are as follows: Tox= 100, NA-105 cm, n=580 cm-/V- sec, VTON=0.7V. a) Calculate the value of the oxide capacitance per unit area Cox. Place your answer in units of F/cm and fF/m. b) Find the value of K,' in units of A/V. c) Find the value of the body bias coefficient y. 7. An nFET process is described by the parameters Kn' = 110 A/V and VTon=0.7 V. The voltages are measured to be VGSn=2V and VSBn-OV. a) A FET with an aspect ratio of 4 has a drain current of 340 A flowing through it. Find the drain-source voltage Vosn b) A different FET is biased with Vosn=2V and VSBn-OV, and the current is measured as 440 A. Find the gate source voltage VGsn, if the aspect ratio is known to be 8. 8. Evaluate the output of the pass transistor, assume Vtn and Vtp as threshold voltage of nMOS and PMOS, respectively. Neglecting body effect. (a) (b) (C) VDD VDDI 2 GND Vo Vo VODI VDD VDD VDD VDD VDD I (d) VDO VO Vo 9. Evaluate the output of pass transistor, neglecting body effect. (a) (c) VDD AA Fu vo GND VDD GND VDD Vo (d) VDD A GND Vout GND VDD + GND Vo GND VDD 10. Suppose VDD=1.2 V and Vth=0.4V. Determine VouT in Figure below for the following input, neglect body effect. (a) Vin-OV, (b) Vin=0.6V, (c) Vin=0.9V, (d) Vin=1.2V. Vo 11. Sketch a transistor level schematic for a compound CMOS logic gates for each of the following function. i) Y=(ABC+D)' ii) Y=[(AB+C)D]' iii) Y=[AB+C(A+B)]' 12) Use transmission gate and NMOS Pass transistor to generate following function. i) Y=AB'+A'B ii) Y=A'B'+AB iii) Y=AB+BC+AC 13) Consider the design of a CMOS compound OAI gate computing F=[(A+B)C]' a) Sketch a transistor level schematic b) sketch a stick diagram c) estimate the area from the stick diagram d) layout your gate with a CAD tool unit sized transistors e) compare the layout size to the estimated area. 14) Consider the design of a CMOS compound OAI gate computing F=[(A+B)(C+D)]' a) Sketch a transistor level schematic b) sketch a stick diagram c) estimate the area from the stick diagram d) layout your gate with a CAD tool unit sized transistors e) compare the layout size to the estimated area.