1. Consider the computation of the logic function NAND. We can represent this computation in diagrams using the NAND gate symbol shown here. Figure 2.5 in the textbook shows a representation of the NAND computation at a lower level of abstraction than the gate symbol. What is shown in that textbook figure for NAND that is omitted at the higher level of abstraction used when depicting the NAND computation using the gate symbol shown here? List the lower level symbols omitted when using the gate symbol. a. b. This symbol is the pinout diagram representation of the SN74HTCOON quadruple 2- input NAND chip in your lab kit, or 7400 for short. 7400 Quad 2 Input NAND Is the level of abstraction of the 7400 pinout diagram higher, lower, or the same with respect to a set of four NAND gate symbols Is the level of abstraction of the logic signal input pins for one gate of the 7400 pinout diagram higher, lower, or the same with respect to the logic signal inputs for Figure 2.5? c. d. Is the level of abstraction of the VCC and GND power and ground pins for the 7400 pinout diagram higher, lower, or the same as the + voltage (Vdd) and 0 volts connections for the NAND circuit in Figure 2.5 1. Consider the computation of the logic function NAND. We can represent this computation in diagrams using the NAND gate symbol shown here. Figure 2.5 in the textbook shows a representation of the NAND computation at a lower level of abstraction than the gate symbol. What is shown in that textbook figure for NAND that is omitted at the higher level of abstraction used when depicting the NAND computation using the gate symbol shown here? List the lower level symbols omitted when using the gate symbol. a. b. This symbol is the pinout diagram representation of the SN74HTCOON quadruple 2- input NAND chip in your lab kit, or 7400 for short. 7400 Quad 2 Input NAND Is the level of abstraction of the 7400 pinout diagram higher, lower, or the same with respect to a set of four NAND gate symbols Is the level of abstraction of the logic signal input pins for one gate of the 7400 pinout diagram higher, lower, or the same with respect to the logic signal inputs for Figure 2.5? c. d. Is the level of abstraction of the VCC and GND power and ground pins for the 7400 pinout diagram higher, lower, or the same as the + voltage (Vdd) and 0 volts connections for the NAND circuit in Figure 2.5