1- Consider the following logic gate diagram. a. What is the logic function representing the design? b. Using circuitverse simulator, implement and verify the logic design by using a testbench. c. Optimize the circuit using k-map. What is L, G, GN cost? d. Reduce the number of leterals to the minum. What is L, G, GN cost? e. Using circuitverse simulator, implement and verify the optimized logic design by using a testbench