1) Consider the hypothetical processor with instruction format seen below: 15 3 4 Opcode Address In class, we saw an example that considered the following instruction op-codes: 0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory %3D For this question, consider two additional op-codes: 0011 = Load AC from 1/0 device 0111 = Store AC to 1/0 device %3D For these new op-codes, the address field in the instruction refers to some external I/0 device, rather than a location in main memory. Show the execution for a program that does the following: 1. Load AC from device 5 (address 705). 2. Add contents of memory location 305. 3. Store AC to device 6 (address 706). In your answer, it is enough to show the contents of the registers at each step. The initial state of the CPU, in the same format we saw in class, can be seen below. You must fill in the memory and register values for this initial fetch stage and all remaining instruction cycles. Fetch Stage CPU registers Memory 300 300 PC 301 302 303 000 AC IR 0000 0003 Device 5 304 0000 305 0002 0000 Device 6 Fetch Stage Execute Stage Instruction Format: CPU Registers 30 0 PC Memory 300 19 4 0 301 5 9 4 1 302 2 9 4 1 CPU Registers 301 PC 000 3 AC 1940 IR Memory 300 1 9 4 0 AC 301 5 9 4 1 302 2 9 41 Example 1940 IR 940 0 0 0 3 9410 0 0 2 940 0 0 0 3 941 0 0 0 2 Sample program fragment: b = a + b Step 1 Step 2 Memory 300 19 4 0 301 5 9 4 1 302 2 9 4 1 CPU Registers 30 1 PC 0 00 3 AC 301 5 9 4 1 5 9 4 1 IR Memory 300 1 9 40 CPU Registers 30 2 PC 0 0 05AC 5 9 4 1R Partial list of opcodes: Ob0001 = 0x1 = Load AC from memory 302 2 9 4 1 940 0 0 0 3 941 0 0 0 2 940 0 00 3 941 0 0 0 2 Ob0010 = Ox2 = Store AC to memory Ob0101 = Ox5 = Add to AC from memory %3D %3D Step 3 Step 4 CPU Registers 30 2 PC 0 00 5 AC 301 5 9 4 1 29 4 1 IR CPU Registers ]C 0 0 05AC 29 4 1 IR Memory 300 19 4 0 301 5 9 4 1 Memory 3001 9 40 Values are in hexadecimal 302 2 9 4 1 302 2 9 4 1 How many fetch-execute cycles? 940 0 0 0 3 941 0 0 0 5 940 0 0 0 3 941 0 0 0 2 Step 6 Step 5