Answered step by step
Verified Expert Solution
Link Copied!

Question

1 Approved Answer

1. Consider the modification of the master-slave latch pair given in Fig. 1. a) Under a regularly changing clock CK, specify the sequence y1, 42,

image text in transcribed

1. Consider the modification of the master-slave latch pair given in Fig. 1. a) Under a regularly changing clock CK, specify the sequence y1, 42, 43, 44 of output signals appearing at Q at the end of the first four clock cycles, given that the input signals arriving at D during these clock cycles are 1,0,0 and 1, respectively. Assume that the initially latched value in the first latch of the pair is Q1 = 1 and it is Q2 = 0 in the second. The input is supposed to be stable during the second half of each clock cycle, and the outputs, too, will be recorded in the second half of the clock cycles only. 02 CK Figure 1: A modified master-slave latch. b) Will the output of the circuit remain stable during the entire clock cycle each time for every input, regardless of the initially latched values in Q1 and Q2? If so, explain why. If not, provide a counter-example input sequence from D on which the output Q only sets in during the second half of some clock cycle. Do not count propagation delays. c) Starting from the given initial state Q1 = 1, Q2 = Q = 0, is there a non-empty sequence of inputs that will turn the output Q down to 0 in the end? Specify such a sequence if it exists, or explain why it does not exist. 1. Consider the modification of the master-slave latch pair given in Fig. 1. a) Under a regularly changing clock CK, specify the sequence y1, 42, 43, 44 of output signals appearing at Q at the end of the first four clock cycles, given that the input signals arriving at D during these clock cycles are 1,0,0 and 1, respectively. Assume that the initially latched value in the first latch of the pair is Q1 = 1 and it is Q2 = 0 in the second. The input is supposed to be stable during the second half of each clock cycle, and the outputs, too, will be recorded in the second half of the clock cycles only. 02 CK Figure 1: A modified master-slave latch. b) Will the output of the circuit remain stable during the entire clock cycle each time for every input, regardless of the initially latched values in Q1 and Q2? If so, explain why. If not, provide a counter-example input sequence from D on which the output Q only sets in during the second half of some clock cycle. Do not count propagation delays. c) Starting from the given initial state Q1 = 1, Q2 = Q = 0, is there a non-empty sequence of inputs that will turn the output Q down to 0 in the end? Specify such a sequence if it exists, or explain why it does not exist

Step by Step Solution

There are 3 Steps involved in it

Step: 1

blur-text-image

Get Instant Access to Expert-Tailored Solutions

See step-by-step solutions with expert insights and AI powered tools for academic success

Step: 2

blur-text-image

Step: 3

blur-text-image

Ace Your Homework with AI

Get the answers you need in no time with our AI-driven, step-by-step assistance

Get Started

Recommended Textbook for

Database And Expert Systems Applications 23rd International Conference Dexa 2012 Vienna Austria September 2012 Proceedings Part 1 Lncs 7446

Authors: Stephen W. Liddle ,Klaus-Dieter Schewe ,A Min Tjoa ,Xiaofang Zhou

2012th Edition

3642325998, 978-3642325991

More Books

Students also viewed these Databases questions

Question

What are the purposes of promotion ?

Answered: 1 week ago

Question

What were your most important educational experiences?

Answered: 1 week ago

Question

Which personal relationships influenced you the most?

Answered: 1 week ago