1. Consider the modification of the master-slave latch pair given in Fig. 1. a) Under a regularly changing clock CK, specify the sequence y1, 42, 43, 44 of output signals appearing at Q at the end of the first four clock cycles, given that the input signals arriving at D during these clock cycles are 1,0,0 and 1, respectively. Assume that the initially latched value in the first latch of the pair is Q1 = 1 and it is Q2 = 0 in the second. The input is supposed to be stable during the second half of each clock cycle, and the outputs, too, will be recorded in the second half of the clock cycles only. 02 CK Figure 1: A modified master-slave latch. b) Will the output of the circuit remain stable during the entire clock cycle each time for every input, regardless of the initially latched values in Q1 and Q2? If so, explain why. If not, provide a counter-example input sequence from D on which the output Q only sets in during the second half of some clock cycle. Do not count propagation delays. c) Starting from the given initial state Q1 = 1, Q2 = Q = 0, is there a non-empty sequence of inputs that will turn the output Q down to 0 in the end? Specify such a sequence if it exists, or explain why it does not exist. 1. Consider the modification of the master-slave latch pair given in Fig. 1. a) Under a regularly changing clock CK, specify the sequence y1, 42, 43, 44 of output signals appearing at Q at the end of the first four clock cycles, given that the input signals arriving at D during these clock cycles are 1,0,0 and 1, respectively. Assume that the initially latched value in the first latch of the pair is Q1 = 1 and it is Q2 = 0 in the second. The input is supposed to be stable during the second half of each clock cycle, and the outputs, too, will be recorded in the second half of the clock cycles only. 02 CK Figure 1: A modified master-slave latch. b) Will the output of the circuit remain stable during the entire clock cycle each time for every input, regardless of the initially latched values in Q1 and Q2? If so, explain why. If not, provide a counter-example input sequence from D on which the output Q only sets in during the second half of some clock cycle. Do not count propagation delays. c) Starting from the given initial state Q1 = 1, Q2 = Q = 0, is there a non-empty sequence of inputs that will turn the output Q down to 0 in the end? Specify such a sequence if it exists, or explain why it does not exist