1. Consider the pipelined MIPS datapath in Figure 4.65 and the instruction sequence shown below. In the spaces provided, give the name of the pipeline register (such as "IF/ID") from which the indicated operands are routed to the ALU. 

addi $2, $0, 0x7800 addi $3, $0, 0x3400 add $4, $3, $2 ori $5, $3, 40 sub $6, $2, $5 

$3: __________________ $2: __________________ $3: __________________ 40: __________________ $2: __________________ $5: __________________ 

Please give an explanation of all answers. Thanks in advance!

F.Flush Hazard detection uni ID/EX MEMWB Control u 0- X IFIID Shift left 2 n Registers E M Data nstruction PC ALU memory memory Sign extend Fowarding unit FIGURE 4.65 The final datapath and control for this chapter. Note that this is a stylized figure rather than a detailed datapath, so its missing the ALUsrc Mux from Figure 4.57 and the multiplexor controls from Figure 4.51 F.Flush Hazard detection uni ID/EX MEMWB Control u 0- X IFIID Shift left 2 n Registers E M Data nstruction PC ALU memory memory Sign extend Fowarding unit FIGURE 4.65 The final datapath and control for this chapter. Note that this is a stylized figure rather than a detailed datapath, so its missing the ALUsrc Mux from Figure 4.57 and the multiplexor controls from Figure 4.51