1. (Correctness) (6 points) Pipelined Processor 1. Dr. Mario has just learned about pipelined CPUs in CSE 141. He is excited about the prospect of taking an existing multicycle design and retrofitting it to a pipelined implementation. Dr. Mario is fascinated by processors with very high frequency. He proposes a 7 stage pipeline, where stage IF and M are split into two stages each (10, 11, MO, M1). Unfortunately, Dr. Mario is a big talker, but he really doesn't know what he's talking about (he's just a computer programmer after all). Can you help him answer the following questions (in this case, Dr. Mario is fictional so it would not be an Al violation to do the job for him). a) Draw a pipeline diagram for this machine executing the following sequence of instructions (list the instruction on the left and identify the stages and cycle for each instruction). Dr. Mario has filled out the first row for you. Assume all branches are not taken and that data forwarding logic exists so results may be used before they are written to the register file. lw r3, r2, 0(rl) addiu r5, r4, 4 beg r7, r6, loop and r10, r9, r8 or r13, r8, r9 xor r15, r15, r14 bne r10, r5, someplace lui r6, 0x1000 ori r10, Oxfeed Instruction CO ci C2 c3 C4 c5 c7 C8 C9 c10 c11 c12 c13 c14 c15 lw r3, r2, 0(ri) 10 11 RF EX MO M1 WB 1. (Correctness) (6 points) Pipelined Processor 1. Dr. Mario has just learned about pipelined CPUs in CSE 141. He is excited about the prospect of taking an existing multicycle design and retrofitting it to a pipelined implementation. Dr. Mario is fascinated by processors with very high frequency. He proposes a 7 stage pipeline, where stage IF and M are split into two stages each (10, 11, MO, M1). Unfortunately, Dr. Mario is a big talker, but he really doesn't know what he's talking about (he's just a computer programmer after all). Can you help him answer the following questions (in this case, Dr. Mario is fictional so it would not be an Al violation to do the job for him). a) Draw a pipeline diagram for this machine executing the following sequence of instructions (list the instruction on the left and identify the stages and cycle for each instruction). Dr. Mario has filled out the first row for you. Assume all branches are not taken and that data forwarding logic exists so results may be used before they are written to the register file. lw r3, r2, 0(rl) addiu r5, r4, 4 beg r7, r6, loop and r10, r9, r8 or r13, r8, r9 xor r15, r15, r14 bne r10, r5, someplace lui r6, 0x1000 ori r10, Oxfeed Instruction CO ci C2 c3 C4 c5 c7 C8 C9 c10 c11 c12 c13 c14 c15 lw r3, r2, 0(ri) 10 11 RF EX MO M1 WB
