1. Describe the trade-offs of increasing each of the following cache parameters while keeping the others the same: (a) block size (b) associativity (c) cache size 2. Is the miss rate of a two-way set associative cache always, usually, occasionally, or never better than that of a direct mapped cache of the same capacity and block size? Explain. 3. A cache has the following parameters: b, block size given in numbers of words; S, number of sets; N, er of address bits. (a) In terms of the parameters described, what is the cache capacity, C? (b) In ters of the parameters described, what is the totaber of bits required to store the tags? (c) What are S and N for a fully associative cache of capacity C words with block size b? (d) What is S for a direct mapped cache of size C words and block size b? 4. A 16-word cache has the parameters given in the previous problem. Consider the following repeating sequence of lw addresses (given in hexadecimal) 40 44 48 4C 70 74 78 7C 80 84 88 8C 90 94 98 9C 0 4 8 C 10 14 18 1C 20 Assuming least recently used (LRU) replacement for associative caches, determine the effective miss rate if the sequence is input to the following caches, ignoring startup effects (i.e., compulsory misses) (a) direct mapped cache, b1 word (b) fully associative cache, b = 1 word (c) two-way set associative cache, b = 1 word (d) direct mapped cache, b 2 words