1. Design a 16 KB (byte addressable) RAM from 256 4 bit chips. Each chip has a single select-line. The chip is enabled if the select-line is activated. You need to show the components, the connections and size of each component to receive the full credit.

2. You have been assigned to design a 8M x 32 bit memory board. You may use only 256K x 8 bit RAM chips with full parallel addressing.

a. How many bits are required in the Address Bus of the whole board?

b. How many address pins are required per chip?

c. How many data I/O pins are required per chip?

d. How many of the system address lines must be split-off and decoded for input into Chip-Enable pins.