$1.$ Design a $4-1$ MUX where the inputs are A$,$B$,$C$,$ and D in order. let the output be :

A at S$0=0,$ S$1=1,$

B at S$0=1,$ S$1=0,$

C at S$0=0,$ S$1=0,$

D at S$0=1,$ S$1=1.$

$2.$ Build a SR$-$latch circuit and explain how it works.

$3.$ The $4-$bit abcd number will be incremented$/$subtracted depending on the selector. When S$=0,$ the value of the number will increase by $2,$ while when S$=1,$ the value of the number will decrease by $2.$ For example, if the number abcd is $9,$ it will appear as $11$ when S$=0$ and $7$ when S$=1.$ Design the required circuit in a hierarchical structure using one$-$bit full adders.

NOTE: For all questions

Verify the operation of your circuit using Verilog, MATLAB or any other sim. program?