1. Design a FSM using a State Diagram that takes as an input a serial bit stream and outputs Logic 1" whenever the input sequence is" 101". Overlaps must be considered, that is for example, if the input bit stream is 1110101100 where the right most bit is the first input to the FSM, then the output will be a "1" after the 6th bit input, then be a "o" for the next c and then a "1" for the next clock. The output will remain a "O" for the remainder of t bit stream. Assume the Input (X) is a single binary bit and is synchronous to is a "O" in the initial reset (Rst) state. The output is Y. You must Iabel ll states, the output in each state and all transitions from state to state to get full credit. Show the initial state by drawing a "Rst" arrow into it. (20 pts) y bit and is synchronous to the FSM clock and