1. Design a synchronous up-down counter that has the following up and down sequences: (0, 1, 2, 3, 4, 5, 6, 7 & repeat) and (0, 7, 6, 5, 4, 3, 2, 1 & repeat). The counter has a 1-bit control input (UD), such that the counter counts upward for UD = 0 and counts downward when UD 1. Use negative edge triggered D-type flip-flops and logic gates to implement the up-down counter design. (a) Start your design with a state table. (b) (c) (5 marks) Develop the next state equations and simplify them if required. Show your complete work. Implement and draw the synchronous counter circuit. (13 marks) (7 marks) 1. Design a synchronous up-down counter that has the following up and down sequences: (0, 1, 2, 3, 4, 5, 6, 7 & repeat) and (0, 7, 6, 5, 4, 3, 2, 1 & repeat). The counter has a 1-bit control input (UD), such that the counter counts upward for UD = 0 and counts downward when UD 1. Use negative edge triggered D-type flip-flops and logic gates to implement the up-down counter design. (a) Start your design with a state table. (b) (c) (5 marks) Develop the next state equations and simplify them if required. Show your complete work. Implement and draw the synchronous counter circuit. (13 marks) (7 marks)