8. (a) Draw the state transition diagram for a three-bit counter that has the following counting sequence: 0,1,2,4,6,7,3,5,0,1... repeats. (b) What is the MOD number of the counter? (c) Design and implement a synchronous counter to generate the counting sequence in (a) using negative-edge- triggered JK flip-flops with a minimum number of logic gates. (d) If the counter is initially at 1012, what count will it hold after 3673 pulses?