1. Draw the logic diagram of the digit circuit specified by the following Verilog description: module Circuit A (A, B, C, D, F); input A, B, C, D; output F; wire w, x, y, z, a, d; or (x, B, C, d); and (y, a,C); and (w, z,B); and (z, y, A); or (F, x, w); not (a, A); not (d, D); endmodule module Circuit B (y1, y2, y3, a, b); output y1, y2, y3; input a, b; assign yl-al| b; and (y2, a, b); assign y3-a && b; endmodule