1. Each of the ALUs in the block diagram can perform eight operations: GT, LT, GTE, LTE, NE, EQ, Shift left, Shift right. Each of the inputs is 16 bit wide. The operations performed by the ALU are given below for each rows are given below a. b. c. d. First row: GT, GTE, LT, LTE Second row: Shift left, Shift right, EQ, NE Third row: LTE, LT, GTE, GT Fourth row: NE, EQ, Shift right, Shift left ALU 1, ALU 12 ALU 13 ALU 22 ALU 3.2 ALU 42 The ALUs in the edges can communicate with three of its immediate neighbors. Whereas the other ALUs can communicate with immediate four. The MUXes have their own selector input (Not drawn in the block diagram. Consider an appropriate selector input width for each of the MUX) The MUXes repeat after each rows of ALU. Assume any form of connection between the ALUs and clearly mention that. For example ALU 2, 1 gets its inputs from ALU 1,1 and ALU 2,2 and saving the output to ALU 3,1. The outputs from the extreme bottom ALUs are 16 bit. If the output is less than 16 bit then concatenate '0' is the necessary bit positions. Submit Block diagram (5) Behavioral VHDL code with comments placed appropriately. (5) . 1. Each of the ALUs in the block diagram can perform eight operations: GT, LT, GTE, LTE, NE, EQ, Shift left, Shift right. Each of the inputs is 16 bit wide. The operations performed by the ALU are given below for each rows are given below a. b. c. d. First row: GT, GTE, LT, LTE Second row: Shift left, Shift right, EQ, NE Third row: LTE, LT, GTE, GT Fourth row: NE, EQ, Shift right, Shift left ALU 1, ALU 12 ALU 13 ALU 22 ALU 3.2 ALU 42 The ALUs in the edges can communicate with three of its immediate neighbors. Whereas the other ALUs can communicate with immediate four. The MUXes have their own selector input (Not drawn in the block diagram. Consider an appropriate selector input width for each of the MUX) The MUXes repeat after each rows of ALU. Assume any form of connection between the ALUs and clearly mention that. For example ALU 2, 1 gets its inputs from ALU 1,1 and ALU 2,2 and saving the output to ALU 3,1. The outputs from the extreme bottom ALUs are 16 bit. If the output is less than 16 bit then concatenate '0' is the necessary bit positions. Submit Block diagram (5) Behavioral VHDL code with comments placed appropriately