Describe the modifications to the single clock cycle datapath that would be needed to implement the jalr instruction (jump and link register - of the text), and give the control signal settings that would be required for this instruction. Jump and link register 0 rs 0 rd 0 9 jalr rs, rd. 6 5 5 5 5 6 Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31). Jump register rs 0 jr rs 6 5 15 8 6 Unconditionally jump to the instruction whose address is in register rs. Trap Instructions Trap if equal 0 rs rt 0 Ox34 teq rs, rt 5 5 10 6 If register rs is equal to register rt, raise a Trap exception. Trap if equal immediate 1 rs imm teqi rs, imm 6 5 5 16 If register rs is equal to the sign-extended value imm, raise a Trap exception. Trap if not equal 0 rs rt Ox36 teq rs, rt 6 5 5 10 If register rs is not equal to register rt, raise a Trap exception. Trap if not equal immediate 1 rs teqi rs, imm Oxe imm 6 5 5 16 If register rs is not equal to the sign-extended value i mm, raise a Trap exception.