1) How many clock cycles would be required to execute this sequence on the multi-cycle data path if each stage that is used requires one clock cycle to complete?

2) What would be the CPU clock rate in Hz for this sequence if instead the single-cycle datapath is used?

3) What would be the CPU clock rate in Hz for this sequence if our 5-stage MIPS pipeline is used?

4) How many clock cycles would be required to execute this sequence using the 5-stage MIPS pipeline?

2. Assume that our MIPS instruction subset is redefined to contain only the following nstructions Instruction Instruction fetch Instructio ALU execute Data Memory Write back decode 300 ps 300 ps 300 ps 300 ps access 150 ps 150 150 R-format 250 ps 250 250 500 ps 500 ps 200 ps lw SW bne The table lists the times required for each step within each instruction. Recall that with the single-cycle and multi-cycle datapaths, the steps with 0 duration are not used. But with the pipeline, everv instruction must pass through all 5 pipeline stages. Assume that all registers contain 0 initially. The following instruction sequence is to be executed or $2,S0,S0 and S7,S3.S11 sub $8,S8,S3 sw $5,0x800 (S2) lwS7,0x804(S0) add S8, S8, S8 bne S7, S4, 0x040 2. Assume that our MIPS instruction subset is redefined to contain only the following nstructions Instruction Instruction fetch Instructio ALU execute Data Memory Write back decode 300 ps 300 ps 300 ps 300 ps access 150 ps 150 150 R-format 250 ps 250 250 500 ps 500 ps 200 ps lw SW bne The table lists the times required for each step within each instruction. Recall that with the single-cycle and multi-cycle datapaths, the steps with 0 duration are not used. But with the pipeline, everv instruction must pass through all 5 pipeline stages. Assume that all registers contain 0 initially. The following instruction sequence is to be executed or $2,S0,S0 and S7,S3.S11 sub $8,S8,S3 sw $5,0x800 (S2) lwS7,0x804(S0) add S8, S8, S8 bne S7, S4, 0x040