1. How many instructions are in the pipeline in any cycle? Assume you have infinite instructions and no data and control flow dependencies

2. How many times is the RegWrite control signal of a particular instruction stored in a register? Why cant we feed the RegWrite signal from the control to the register file directly?

3.

Assume the following instruction sequence

Instruction fetch time (in cycles)	instruction
1	add x17, x3, x4
2	addi x18, x3, 1
3	lw x19, x6, 0
4	add x20, x5, x3
5	add x21, x2, x4
6	addi x22, x7, 2

a) What source registers are read at time = 5?

b) What destination register is written at time = 5?

c) At time=6, what instructions are currently in the pipeline?

d) In which cycle(s) is MemRead=1?

e) In which cycle(s) is the ALUSrc=1?