(1) Implement a 4-bit counter using the Verilog module feature of Xilinx ISE. (2) Create an appropriate test file to simulate the following functions: a. Clock period is 200 nS; b. At 100 nS, load number 4 into the counter; c. Starting at 300 nS: count UP 1 step every 200 nS, until the counter output reaches 7 at 700 nS; d. Starting at 900 nS, count DOWN 1 step every 200 nS, until the counter output reaches 4; e. Stop simulation after the counter output reaches 4. (3) Run the simulation and generate the output waveforms to demonstrate that your design works correctly. Report the time interval that the counter output reaches 4. Report: Combine following three files in one pdf and upload in Blackboard (1) The Verilog file of your design including your name and eRaider ID added in the comment section of the file. (2) Your test file; (3) Your waveform printou