1. Implement the following circuit to test the characteristics of a D flip flop. Note: Using a clock input to operate the flip-flop is rather quickly. You may wish to select the slow motion of the clock OR to use a simple binary input device instead of a clock input device. Verify the flip flop state table. Q(t+1) = D, is the characteristic equation. 1 Characteristic Table Excitation Table Q(t) Q(t+1) D D Q(+1) Operation Reset ================== 0 0 0 0 1 1 Set 0 1 1 1 0 0 1 1 1 EESEEEEEEE D Flip Flop Test CLKIO When 1. pin state to 1 Set When 1, clock effective O When 1. pin state to o Reset o Questions: Is a D flip-flop positive or negative edge triggered? What happens when the Set pin is set to one? What happens when the Reset pin is set to one? Does it matter what the D input is when either Set or Reset is one? 2. Experimentally verify the JK flip-flop state table with the following circuit. Is the JK flip-flop positive or negative edge triggered? Verify the Characteristic table. JK Flip Flop Test CLK O 0 When 1. pin state to 1 O When 0, clock ineffective lo When 1. pin state to O 0 Reference: The characteristic equation of the JK flip-flop is Q(t+1) = JQ'(t) + K'Q(t). Characteristic Table Excitation Table J K Q(t+1) Operation Q(t) Q(t+1) J K 0 0 Q(t) No Change 0 0 OX 010 Reset 0 1 1 x 101 Set 1 0 X1 11 Q'(t) Complement 1 1 3. Design a 3 bit counter which follows the sequence 0 -> 2 -> 3 -> 4 -> 7 -> 0. Note: The following are required for the lab Assignment: Follow the sequential design procedure which is presented in the lab lecture notes. To make marking easier, route all the unused states to state 7. Use JK flip-flops in your counter circuits. Hand in: . Show your design steps and the resulting circuit in Logisim. Describe your testing procedures. 1. Implement the following circuit to test the characteristics of a D flip flop. Note: Using a clock input to operate the flip-flop is rather quickly. You may wish to select the slow motion of the clock OR to use a simple binary input device instead of a clock input device. Verify the flip flop state table. Q(t+1) = D, is the characteristic equation. 1 Characteristic Table Excitation Table Q(t) Q(t+1) D D Q(+1) Operation Reset ================== 0 0 0 0 1 1 Set 0 1 1 1 0 0 1 1 1 EESEEEEEEE D Flip Flop Test CLKIO When 1. pin state to 1 Set When 1, clock effective O When 1. pin state to o Reset o Questions: Is a D flip-flop positive or negative edge triggered? What happens when the Set pin is set to one? What happens when the Reset pin is set to one? Does it matter what the D input is when either Set or Reset is one? 2. Experimentally verify the JK flip-flop state table with the following circuit. Is the JK flip-flop positive or negative edge triggered? Verify the Characteristic table. JK Flip Flop Test CLK O 0 When 1. pin state to 1 O When 0, clock ineffective lo When 1. pin state to O 0 Reference: The characteristic equation of the JK flip-flop is Q(t+1) = JQ'(t) + K'Q(t). Characteristic Table Excitation Table J K Q(t+1) Operation Q(t) Q(t+1) J K 0 0 Q(t) No Change 0 0 OX 010 Reset 0 1 1 x 101 Set 1 0 X1 11 Q'(t) Complement 1 1 3. Design a 3 bit counter which follows the sequence 0 -> 2 -> 3 -> 4 -> 7 -> 0. Note: The following are required for the lab Assignment: Follow the sequential design procedure which is presented in the lab lecture notes. To make marking easier, route all the unused states to state 7. Use JK flip-flops in your counter circuits. Hand in: . Show your design steps and the resulting circuit in Logisim. Describe your testing procedures
