1. Implement this ALU in VHDL: a (7:0) b (7:0) Logic Unit Mux y (7:0) Arithmetic Unit sel (3) cin sel (3:0) Function Transfera Increment a Decrement a Transfer b Increment b Decrement b Add a and b Add a and b with carr Complement a Complement b AND OR NAND NOR XOR Se eration Unit 0001 0010 0011 0100 0101 01 10 | y