1 In a MIPS pipelined datapath, register renaming helps to eliminate a control hazards b write after read data hazards c read after write data hazards d write after write data hazards 2 Pipelines increase CPU performance by decreasing instruction latency a True b False 3 What is the clock rate in a pipelined datapath with stage times shown below IF 305 ps ID 250 ps EX 270 ps MEM 305 ps WB 225 ps a 3 28 GHz b 4 GHz c 3 7 GHz d 4 4 GHz

Question

1  In a MIPS pipelined datapath, register renaming helps to eliminate    a control hazards b write after read data hazards c read after write data hazards d write after write data hazards 2  Pipelines increase CPU performance by decreasing instruction latency  a True b False 3 What is the clock rate in a pipelined datapath with stage times shown below  IF 305 ps ID 250 ps EX 270 ps MEM 305 ps WB 225 ps a 3 28 GHz b 4 GHz c 3 7 GHz d 4 4 GHz

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Question

1. In a MIPS pipelined datapath, register renaming helps to eliminate... a control hazards b write-after-read data hazards c read-after-write data hazards d write-after-write data

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