1. In this question, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies shown in Table 1: IF ID 5Ups350ps 150ps EXMEMWB 300ps200ps 2 Table 1: Latencies of Individual Stages Also, assume that instructions executed by the processor are broken down as shown in Table 2: alu beqlw sw 45% | 20% | 20% | 15% Table 2: Percent of Instruction Execution (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an LW instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit