1. It is required to design a combinational circuit that computes the equation Y=8*X+2, where X is an 5-bit unsigned number. a) Write a Verilog model that describes this circuit in structural style using Verilog HDL primitives. b) Write a Verilog model that describes this circuit using Verilog HDL data flow modeling c) Write a test bench and use Modelsim to verify the functionality of the models in a and b. (Test bench and simulation are required) 1. It is required to design a combinational circuit that computes the equation Y=8*X+2, where X is an 5-bit unsigned number. a) Write a Verilog model that describes this circuit in structural style using Verilog HDL primitives. b) Write a Verilog model that describes this circuit using Verilog HDL data flow modeling c) Write a test bench and use Modelsim to verify the functionality of the models in a and b. (Test bench and simulation are required)